Verification Model Development Engineer

Description:

The Verification IP (VIP) team members develop a suite of Software tools and environments used for the verification of various Arm Hardware IP products. The VIP team has the responsibility for supplying reliable, correct, consistent and documented VIP to design teams spread across the world. We ensure compatibility between remotely designed components by focussing on the correctness of the interfaces between them!

Responsibilities

Our verification IP engineers have responsibility for the architecting, authoring, and testing of our suite of VIP. We work closely with the Arm AMBA architects in the definition of new interface protocols, providing input on the verifiability of various proposals by providing a modelling environment for system level communication. The VIP team has responsibility for supplying reliable, correct, consistent and documented VIP to design teams in offices around the world. This means that we have an international internal customer base requiring support and enhancements!

Job Requirements

Essential Skills & Experience
 

• Must be able to demonstrate a good understanding and experience of object-oriented design and programming using languages such as SystemVerilog, C++, Java or Python
• Experience with Hardware verification methodologies such as OVM or UVM
• Experience in Test bench construction including TB component design and implementation
• Self-driven with the ability to work well individually and as part of a team
   

‘Nice to Have’ Skills & Experience
 

• Experience in using modern day software development techniques and workflows such as Continuous Integration and Continuous Delivery
• Exposure to methodologies such as Unit Test, TDD and automated testing
• Exposure to AMBA, PCI-Express, CCIX, CXL or similar such industry standard protocols
• Perl, Python or other scripting language
• Good university degree (or equivalent) in Computer Science, Mathematics, Engineering or related subject.