Ic Layout Engineer

Description:

A semiconductor company based in the Thames Valley and market leader in imaging applications is looking for an Analog IC Layout Engineer. You will support an experienced team in the creation of layouts of Analog Mixed Signal IC’s in Cadence and Mentor tools for modifications to existing products and develop layout solutions for new products.

• Your responsibilities will include floorplanning, top level layout, top level verification (LVS, DRC, ERC), and top-level LPE.
• You are the right candidate for this role if you are industry degree qualified with industry experience in Analog IC Layout from within a Semiconductor company.
• You have solid understanding of Analog IC Layout, Cadence Virtuoso, capacitive and inductive coupling, matching, verification and evaluation, floorplanning Analog Mixed Signal blocks.
• In addition, you should be familiar with digital techniques such as P&R, timing-driven layout, clock trees, EMIR, and ESD and be able to insert blocks from these processes into Analog Mixed Signal IC Design.