Formal Verification Engineer

Description:

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team at a world-leading Semiconductor Company on topics including the development of next-generation industry-leading CPU and GPU processors.

This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of the company's Systems!

The company is able to support visas and relocation where applicable. This is a great opportunity to work with some of the leading engineers in the industry and provides strong opportunities for future career progression.

Key responsibilities:

• Ownership of verification environment from investigation all the way to verification closure
• Develop, extend, maintain, and improve our SVA Formal testbenches
• Develop, extend, maintain and improve our suite of SVA Protocol Checkers for Formal and Simulation use
• There will be opportunities for improving our verification methodology and mentoring other members of the team
• Close collaboration with other engineering teams leading to high-quality IP that works well in a complete system.

Key Requirements:

• Experience in architecting and implementing formal verification environments for complex IP/module-level designs.
• Experience of property-based model-checking or Formal Property verification
• Practical experience of writing assertions using SystemVerilog Assertions (SVA) with an industry leading formal tool (e.g. Cadence, Mentor, Synopsys tools).
• Ability to quickly understand and apply complex specification details.