Engineer

Description:

The successful candidate will join the IT team based in London, which trades across all the major Asian, EMEA and US markets. The candidate will be expected to provide technical project management and guidance and will be hands-on with infrastructure projects across the EMEA region as well as globally.

Requirements
 

• Degree in Electrical/Electronic Engineering (or related).
• 3+ years' experience in RTL design and verification for FPGAs using Verilog, SystemVerilog or VHDL.
• Experience in FPGA toolchains using Xilinx Vivado (preferred) or Intel Quartus.
• Experience of simulation environments, Modelsim/Questa preferred.
• Experience of using Python within verification frameworks.
• Knowledge of networking protocols, Ethernet, UDP, TCP, etc.
• Knowledge of C++ for writing hardware APIs.
• Exposure to continuous integration and automated test tools.
• Knowledge of Market Data protocol a bonus, but certainly not a requirement.
• Experience with strategy implementation also a bonus.